R-2R 10-Bits MOST-Only D/A Converter - Schematic & Layout
Click here to see post layout INL and DNL simulation results for process corners.

  Test bed for simulation. Top level biasing configuration. Full ladder, consisting of bit slices and an output opamp Full ladder, consisting of bit slices and an output opamp Bit slice, consisting of current divider, path selector and dummy switch Bit slice, consisting of current divider, path selector and dummy switch OpAmp at the output of r-2R ladder  
  toplevel biasing R-2R ladder
 R-2R ladder bit slice
 bit slice D/A opamp

  OpAmp at the output of r-2R ladder Iref, current sink which defines the full scale current of D/A Iref, current sink which defines the full scale current of D/A OpAmp of sink OpAmp of sink Low Drop Out voltage regulator to set 2.1V as D/A reference Low Drop Out voltage regulator to set 2.1V as D/A reference  
  D/A opamp
 sink
 sink sink opamp
 sink opamp LDOv3
 LDOv3

  Bandgap reference to set the reference of LDOv3 Bandgap reference to set the reference of LDOv3 Upper component in bandgap reference Upper component in bandgap reference Diyot component (lower box) in bandgap reference Diyot component (lower box) in bandgap reference 33 pnp transistors connected as diodes reside in diyot_v2 symbol  
  bandgap
 bandgap bandgap upper
 bandgap upper bandgap lower
 bandgap lower diode4bandgap


Özgür Çobanoğlu