- Set all sources with the voltages shown in the
picture. The vdc vol tages of 300mV and 446.68mV were selected to
produce same drain current level which is, in this case, Ids =
41.57µA. The drain-source voltages V2 & V3 have a DC voltage
of Vsweep, which will be swept to produce the characteristic I-V
curve.
- Assign the device sizes and types as shown as well.
- As seen in the upper-left window (Analog Design
Environment), define the Design Variable Vsweep by using "Variables
> Copy From Cell View" menu item and assign 1.5V to it.
- Then as seen in the bottom-left window, select
Vsweep as the design variable to be swapt from 0V to 1.5V which is out
Vdd.
- "Outputs > To Be Plotted > Select On
Schematic" menu iten to select what we want to plot, that is, click on
the drain of nMOS and source of pMOS device so that both the currents
are positive.
- Run the simulation by clicking the green traffic
light-like button on Analog Artist (Analog Design Environment).
- See the output like the one on the bottom-right.
|

Click on the image.
|
Method #1 : Hand
calculation with the values taken from the I-V curve for nMOS device. MuPAD is used as a calculator here.
|
ozgur@olmak:~/Documents/PhD/LLD/130nmDOC/tutparext2>
mupad
*----* MuPAD 2.5.2 -- The Open Computer
Algebra System
/| /|
*----* | Copyright (c) 1997 - 2002
by SciFace Software
|
*--|-*
All rights reserved.
|/ |/
*----*
>> lamda := (Id1-Id2) / ((Vds1-Vds2)*K*(Vgs-Vth)^2)
Id1 - Id2
----------------------------
2
K (Vgs - Vth) (Vds1 - Vds2)
>> K := 0.003291087727: # from part
1 #
>> Vth := 0.2120892994: # from part
1 #
>> Vgs := 0.3: # I set it by myself in the schematic #
>> Id1 := 30.7799*10^-6: # from the marker A #
>> Id2 := 39.8631*10^-6: # from the marker B #
>> Vds1 := 0.36: # from the marker A #
>> Vds2 := 1.31757: # from the marker B #
>> lamda
0.3729455282
>> # This calculation was for the nMOS transistor #
>> _
|

Click on the
image.
|
|
| Hand
calculation with the values taken from the I-V curve for pMOS device. MuPAD is used as a calculator here.
So, according to the values, a pMOS device in this technology is ~4
times better (not sensitive to changes in Vds), in case, channel length
effect is important. |
ozgur@olmak:~/Documents/PhD/LLD/130nmDOC/tutparext2>
mupad
*----* MuPAD 2.5.2 -- The Open Computer
Algebra System
/| /|
*----* | Copyright (c) 1997 - 2002
by SciFace Software
|
*--|-*
All rights reserved.
|/ |/
*----*
>> lamda := (Id1-Id2) / ((Vds1-Vds2)*K*(Vgs-Vth)^2)
Id1 - Id2
----------------------------
2
K (Vgs - Vth) (Vds1 - Vds2)
>> K := 0.0006429193863: # from part
1 #
>> Vth := 0.2010996077: # from part
1 #
>> Vgs := 0.44668: # I set it by myself in the schematic #
>> Id1 := 37.6354*10^-6: # from the marker A #
>> Id2 := 40.9772*10^-6: # from the marker B #
>> Vds1 := 0.507796: # from the marker A #
>> Vds2 := 1.34209: # from the marker B #
>> lamda
0.1033040707
>> _
>> # This calculation was for the pMOS transistor #
>> _
|

Click on the
image.
|
|