NA62

The future NA62 experiment at CERN SPS will study the rare decay of the K⁺ particles. Owing to the extremely low probability of the event, a very high beam rate is required. Silicon Pixel Detectors ( SPD ) have been chosen for the tracking of the particles in the area close to the target. I am working on the design of the readout chip for the SPDs. The design, still in the phase of specs definition, requires a very good time resolution (200 ps r.m.s.) combined with the capability of sustaining a maximum rate of 1.9 MHz/mm² in term of both data transmission and radiation tolerance. These two requirements make the design very challenging. The ongoing design aims to meet these requirements with a Constant Fraction Discriminator (CFD) for the time walk compensation and a Time to Amplitude Converter (TAC) based Time to Digital Converter (TDC) located in each pixel. A second option, based on Time over Threshold (ToT) time walk compensation and Delay Locked Loop (DLL) based TDC is under design at CERN.

Two prototype ASICs has been designed in a CMOS 0.13 μm technology :

1. GtkTo v1.0 (2007) : test chip to prove the feasibility of an integrated CFD with the required performances. Chip status : designed and tested.

2. GtkTo v2.0 (2009) : test chip with two 45 cells full columns and a 15 cells column, end of column buffers and Single Event Upset (SEU) protected control logic. Chip status : under production.

Links :

• NA62 main web page at CERN

• NA62 web page at INFN Torino

Last modification : May 6, 2009