SET_FLAG DEBUG FALSE
SET_FLAG MODE INTERACTIVE
SET_FLAG STANDALONE_MODE FALSE
SET_PREFERENCE devicefamily spartan6
SET_PREFERENCE device xc6slx16
SET_PREFERENCE speedgrade -3
SET_PREFERENCE package csg324
SET_PREFERENCE verilogsim false
SET_PREFERENCE vhdlsim true
SET_PREFERENCE simulationfiles Behavioral
SET_PREFERENCE busformat BusFormatAngleBracketNotRipped
SET_PREFERENCE outputdirectory C:/Xilinx/Projects/nexys3_phy/ipcore_dir/
SET_PREFERENCE workingdirectory C:/Xilinx/Projects/nexys3_phy/ipcore_dir/tmp/
SET_PREFERENCE subworkingdirectory C:/Xilinx/Projects/nexys3_phy/ipcore_dir/tmp/_cg/
SET_PREFERENCE transientdirectory C:/Xilinx/Projects/nexys3_phy/ipcore_dir/tmp/_cg/_dbg/
SET_PREFERENCE designentry VHDL
SET_PREFERENCE flowvendor Other
SET_PREFERENCE addpads false
SET_PREFERENCE projectname coregen
SET_PREFERENCE formalverification false
SET_PREFERENCE asysymbol false
SET_PREFERENCE implementationfiletype Ngc
SET_PREFERENCE foundationsym false
SET_PREFERENCE createndf false
SET_PREFERENCE removerpms false
SET_PARAMETER Component_Name reply_fifo
SET_PARAMETER Fifo_Implementation Common_Clock_Block_RAM
SET_PARAMETER synchronization_stages 2
SET_PARAMETER synchronization_stages_axi 2
SET_PARAMETER Interface_Type Native
SET_PARAMETER Performance_Options Standard_FIFO
SET_PARAMETER Input_Data_Width 9
SET_PARAMETER Input_Depth 2048
SET_PARAMETER Output_Data_Width 9
SET_PARAMETER Output_Depth 2048
SET_PARAMETER Enable_ECC false
SET_PARAMETER Use_Embedded_Registers false
SET_PARAMETER Reset_Pin false
SET_PARAMETER Enable_Reset_Synchronization true
SET_PARAMETER Reset_Type Asynchronous_Reset
SET_PARAMETER Full_Flags_Reset_Value 0
SET_PARAMETER Use_Dout_Reset false
SET_PARAMETER Dout_Reset_Value 0
SET_PARAMETER Almost_Full_Flag false
SET_PARAMETER Almost_Empty_Flag false
SET_PARAMETER Valid_Flag true
SET_PARAMETER Valid_Sense Active_High
SET_PARAMETER Underflow_Flag false
SET_PARAMETER Underflow_Sense Active_High
SET_PARAMETER Write_Acknowledge_Flag false
SET_PARAMETER Write_Acknowledge_Sense Active_High
SET_PARAMETER Overflow_Flag false
SET_PARAMETER Overflow_Sense Active_High
SET_PARAMETER Inject_Sbit_Error false
SET_PARAMETER Inject_Dbit_Error false
SET_PARAMETER Use_Extra_Logic false
SET_PARAMETER Data_Count false
SET_PARAMETER Data_Count_Width 11
SET_PARAMETER Write_Data_Count false
SET_PARAMETER Write_Data_Count_Width 11
SET_PARAMETER Read_Data_Count false
SET_PARAMETER Read_Data_Count_Width 11
SET_PARAMETER Disable_Timing_Violations false
SET_PARAMETER Read_Clock_Frequency 1
SET_PARAMETER Write_Clock_Frequency 1
SET_PARAMETER Programmable_Full_Type No_Programmable_Full_Threshold
SET_PARAMETER Full_Threshold_Assert_Value 2046
SET_PARAMETER Full_Threshold_Negate_Value 2045
SET_PARAMETER Programmable_Empty_Type No_Programmable_Empty_Threshold
SET_PARAMETER Empty_Threshold_Assert_Value 2
SET_PARAMETER Empty_Threshold_Negate_Value 3
SET_PARAMETER AXI_Type AXI4_Stream
SET_PARAMETER Clock_Type_AXI Common_Clock
SET_PARAMETER Use_Clock_Enable false
SET_PARAMETER Clock_Enable_Type Slave_Interface_Clock_Enable
SET_PARAMETER Enable_Write_Channel false
SET_PARAMETER Enable_Read_Channel false
SET_PARAMETER ID_Width 4
SET_PARAMETER AXI_Address_Width 32
SET_PARAMETER AXI_Data_Width 64
SET_PARAMETER Enable_AWUSER false
SET_PARAMETER AWUSER_Width 1
SET_PARAMETER Enable_WUSER false
SET_PARAMETER WUSER_Width 1
SET_PARAMETER Enable_BUSER false
SET_PARAMETER BUSER_Width 1
SET_PARAMETER Enable_ARUSER false
SET_PARAMETER ARUSER_Width 1
SET_PARAMETER Enable_RUSER false
SET_PARAMETER RUSER_Width 1
SET_PARAMETER Enable_TDATA false
SET_PARAMETER TDATA_Width 64
SET_PARAMETER Enable_TID false
SET_PARAMETER TID_Width 8
SET_PARAMETER Enable_TDEST false
SET_PARAMETER TDEST_Width 4
SET_PARAMETER Enable_TUSER false
SET_PARAMETER TUSER_Width 4
SET_PARAMETER Enable_TREADY true
SET_PARAMETER Enable_TLAST false
SET_PARAMETER Enable_TSTROBE false
SET_PARAMETER TSTRB_Width 4
SET_PARAMETER Enable_TKEEP false
SET_PARAMETER TKEEP_Width 4
SET_PARAMETER wach_type FIFO
SET_PARAMETER FIFO_Implementation_wach Common_Clock_Block_RAM
SET_PARAMETER FIFO_Application_Type_wach Data_FIFO
SET_PARAMETER Enable_ECC_wach false
SET_PARAMETER Inject_Sbit_Error_wach false
SET_PARAMETER Inject_Dbit_Error_wach false
SET_PARAMETER Input_Depth_wach 16
SET_PARAMETER Enable_Data_Counts_wach false
SET_PARAMETER Programmable_Full_Type_wach No_Programmable_Full_Threshold
SET_PARAMETER Full_Threshold_Assert_Value_wach 1023
SET_PARAMETER Programmable_Empty_Type_wach No_Programmable_Empty_Threshold
SET_PARAMETER Empty_Threshold_Assert_Value_wach 1022
SET_PARAMETER wdch_type FIFO
SET_PARAMETER FIFO_Implementation_wdch Common_Clock_Block_RAM
SET_PARAMETER FIFO_Application_Type_wdch Data_FIFO
SET_PARAMETER Enable_ECC_wdch false
SET_PARAMETER Inject_Sbit_Error_wdch false
SET_PARAMETER Inject_Dbit_Error_wdch false
SET_PARAMETER Input_Depth_wdch 1024
SET_PARAMETER Enable_Data_Counts_wdch false
SET_PARAMETER Programmable_Full_Type_wdch No_Programmable_Full_Threshold
SET_PARAMETER Full_Threshold_Assert_Value_wdch 1023
SET_PARAMETER Programmable_Empty_Type_wdch No_Programmable_Empty_Threshold
SET_PARAMETER Empty_Threshold_Assert_Value_wdch 1022
SET_PARAMETER wrch_type FIFO
SET_PARAMETER FIFO_Implementation_wrch Common_Clock_Block_RAM
SET_PARAMETER FIFO_Application_Type_wrch Data_FIFO
SET_PARAMETER Enable_ECC_wrch false
SET_PARAMETER Inject_Sbit_Error_wrch false
SET_PARAMETER Inject_Dbit_Error_wrch false
SET_PARAMETER Input_Depth_wrch 16
SET_PARAMETER Enable_Data_Counts_wrch false
SET_PARAMETER Programmable_Full_Type_wrch No_Programmable_Full_Threshold
SET_PARAMETER Full_Threshold_Assert_Value_wrch 1023
SET_PARAMETER Programmable_Empty_Type_wrch No_Programmable_Empty_Threshold
SET_PARAMETER Empty_Threshold_Assert_Value_wrch 1022
SET_PARAMETER rach_type FIFO
SET_PARAMETER FIFO_Implementation_rach Common_Clock_Block_RAM
SET_PARAMETER FIFO_Application_Type_rach Data_FIFO
SET_PARAMETER Enable_ECC_rach false
SET_PARAMETER Inject_Sbit_Error_rach false
SET_PARAMETER Inject_Dbit_Error_rach false
SET_PARAMETER Input_Depth_rach 16
SET_PARAMETER Enable_Data_Counts_rach false
SET_PARAMETER Programmable_Full_Type_rach No_Programmable_Full_Threshold
SET_PARAMETER Full_Threshold_Assert_Value_rach 1023
SET_PARAMETER Programmable_Empty_Type_rach No_Programmable_Empty_Threshold
SET_PARAMETER Empty_Threshold_Assert_Value_rach 1022
SET_PARAMETER rdch_type FIFO
SET_PARAMETER FIFO_Implementation_rdch Common_Clock_Block_RAM
SET_PARAMETER FIFO_Application_Type_rdch Data_FIFO
SET_PARAMETER Enable_ECC_rdch false
SET_PARAMETER Inject_Sbit_Error_rdch false
SET_PARAMETER Inject_Dbit_Error_rdch false
SET_PARAMETER Input_Depth_rdch 1024
SET_PARAMETER Enable_Data_Counts_rdch false
SET_PARAMETER Programmable_Full_Type_rdch No_Programmable_Full_Threshold
SET_PARAMETER Full_Threshold_Assert_Value_rdch 1023
SET_PARAMETER Programmable_Empty_Type_rdch No_Programmable_Empty_Threshold
SET_PARAMETER Empty_Threshold_Assert_Value_rdch 1022
SET_PARAMETER axis_type FIFO
SET_PARAMETER FIFO_Implementation_axis Common_Clock_Block_RAM
SET_PARAMETER FIFO_Application_Type_axis Data_FIFO
SET_PARAMETER Enable_ECC_axis false
SET_PARAMETER Inject_Sbit_Error_axis false
SET_PARAMETER Inject_Dbit_Error_axis false
SET_PARAMETER Input_Depth_axis 1024
SET_PARAMETER Enable_Data_Counts_axis false
SET_PARAMETER Programmable_Full_Type_axis No_Programmable_Full_Threshold
SET_PARAMETER Full_Threshold_Assert_Value_axis 1023
SET_PARAMETER Programmable_Empty_Type_axis No_Programmable_Empty_Threshold
SET_PARAMETER Empty_Threshold_Assert_Value_axis 1022
SET_PARAMETER Register_Slice_Mode_wach Fully_Registered
SET_PARAMETER Register_Slice_Mode_wdch Fully_Registered
SET_PARAMETER Register_Slice_Mode_wrch Fully_Registered
SET_PARAMETER Register_Slice_Mode_rach Fully_Registered
SET_PARAMETER Register_Slice_Mode_rdch Fully_Registered
SET_PARAMETER Register_Slice_Mode_axis Fully_Registered
SET_PARAMETER Underflow_Flag_AXI false
SET_PARAMETER Underflow_Sense_AXI Active_High
SET_PARAMETER Overflow_Flag_AXI false
SET_PARAMETER Overflow_Sense_AXI Active_High
SET_PARAMETER Disable_Timing_Violations_AXI false
SET_PARAMETER Add_NGC_Constraint_AXI false
SET_PARAMETER Enable_Common_Underflow false
SET_PARAMETER Enable_Common_Overflow false
SET_PARAMETER enable_read_pointer_increment_by2 false
SET_CORE_NAME FIFO Generator
SET_CORE_VERSION 9.3
SET_CORE_VLNV xilinx.com:ip:fifo_generator:9.3
SET_CORE_CLASS com.xilinx.ip.fifo_generator_v9_3.fifo_generator_v9_3
SET_CORE_PATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v9_3
SET_CORE_GUIPATH C:/Xilinx/14.7/ISE_DS/ISE/coregen/ip/xilinx/primary/com/xilinx/ip/fifo_generator_v9_3/gui/fifo_generator_v9_3.tcl
SET_CORE_DATASHEET http://www.xilinx.com/cgi-bin/docs/ipdoc?c=fifo_generator;v=v9_3;d=pg057-fifo-generator.pdf
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\fifo_generator_v9_3\doc\fifo_generator_v9_3_vinfo.html><fifo_generator_v9_3_vinfo.html>
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\fifo_generator_v9_3\doc\fifo_generator_v9_3_readme.txt><fifo_generator_v9_3_readme.txt>
ADD_CORE_DOCUMENT <C:\Xilinx\14.7\ISE_DS\ISE\coregen\ip\xilinx\primary\com\xilinx\ip\fifo_generator_v9_3\doc\pg057-fifo-generator.pdf><pg057-fifo-generator.pdf>
