--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   17:01:26 02/06/2016
-- Design Name:   
-- Module Name:   C:/Xilinx/Projects/nexys3_phy/command_processor_tb.vhd
-- Project Name:  nexys3_phy
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: command_processor
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

--use std.textio.all;
--use work.txt_util.all;

 
entity command_processor_tb is
end command_processor_tb;
 
 
architecture behavior of command_processor_tb is 
 
    -- component declaration for the unit under test (uut)
 
	component command_processor
	port (
		clk									: in  std_logic;
		command_available					: in  std_logic;
		command_contents					: in  std_logic_vector(31 downto 0);
		command_reply_available			: out std_logic;
		command_reply_contents			: out std_logic_vector(31 downto 0);
		firmware_version					: in  std_logic_vector(15 downto 0);
		GPIO_Switches						: in  std_logic_vector(7 downto 0);
		GPIO_Buttons						: in  std_logic_vector(4 downto 0);
		Disp_seg								: out std_logic_vector(7 downto 0);
		Disp_an								: out std_logic_vector(3 downto 0)
	);
	end component;
    

   --Inputs
   signal clk								: std_logic := '0';
   signal command_available			: std_logic := '0';
   signal command_contents				: std_logic_vector(31 downto 0) := (others => '0');
   signal firmware_version				: std_logic_vector(15 downto 0) := (others => '0');
   signal GPIO_Switches					: std_logic_vector(7 downto 0) := (others => '0');
   signal GPIO_Buttons					: std_logic_vector(4 downto 0) := (others => '0');

 	--Outputs
   signal command_reply_available	: std_logic;
   signal command_reply_contents		: std_logic_vector(31 downto 0);
   signal Disp_seg						: std_logic_vector(7 downto 0);
   signal Disp_an							: std_logic_vector(3 downto 0);
	

   -- Clock period definitions
   constant clk_period : time := 10 ns;
 
begin
 
	-- Instantiate the Unit Under Test (UUT)
	uut: command_processor
	port map (
		clk									=> clk,
		command_available					=> command_available,
		command_contents					=> command_contents,
		command_reply_available			=> command_reply_available,
		command_reply_contents			=> command_reply_contents,
		firmware_version					=> firmware_version,
		GPIO_Switches						=> GPIO_Switches,
		GPIO_Buttons						=> GPIO_Buttons,
		Disp_seg								=> Disp_seg,
		Disp_an								=> Disp_an
	);

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	

      wait for clk_period*10;

      wait for clk_period*100;
		wait until rising_edge(clk);

      -- insert stimulus here
		
		for loopVar in 1 to 5 loop
			case loopVar is
				
				when 1 => command_contents <= x"1" & x"01" & "0000" & "00000000" & "00000000";						-- read GPIO switches and buttons
				
				when 2 => command_contents <= x"1" & x"02" & "0000" & "00000" & "0" & "00" & "11000000";			-- set LED display 0
				
				when 3 => command_contents <= x"1" & x"02" & "0000" & "00000" & "0" & "01" & "11111001";			-- set LED display 1
				
				when 4 => command_contents <= x"1" & x"02" & "0000" & "00000" & "0" & "10" & "10100100";			-- set LED display 2
				
				when 5 => command_contents <= x"1" & x"02" & "0000" & "00000" & "1" & "11" & "10110000";			-- set LED display 3
			end case;
			
			wait until rising_edge(clk);
			command_available <= '1';
			
			wait until rising_edge(clk);
			command_available <= '0';
			
			wait until (command_reply_available = '1');
			
			wait for clk_period*5;
			wait until rising_edge(clk);
		end loop;

      wait;
   end process;

END;
