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vlib work 
vmap work work 

echo "Compiling Core VHDL UNISIM/Behavioral model"
vcom  -work work ../../../message_fifo.vhd
vcom  -work work ../../example_design/message_fifo_exdes.vhd

echo "Compiling Test Bench Files"
vcom -work work ../message_fifo_pkg.vhd
vcom -work work ../message_fifo_rng.vhd 
vcom -work work ../message_fifo_dgen.vhd
vcom -work work ../message_fifo_dverif.vhd
vcom -work work ../message_fifo_pctrl.vhd 
vcom -work work ../message_fifo_synth.vhd 
vcom -work work ../message_fifo_tb.vhd

vsim  -t ps -voptargs="+acc" -L XilinxCoreLib -L unisim work.message_fifo_tb

add log -r /*
do wave_mti.do
#Ignore integer warnings at time 0
set StdArithNoWarnings 1
run 0
set StdArithNoWarnings 0

run -all
