Wrong
-----
EnetStats code should be x"07" not x"08" to allow correct error reporting(?)
Illegal network command code can lead to no reply
Software recovery logic changes mean that attempting to start a second program while a
previous one is still running does not lead to immediate bail-out


To do
-----


2/4/16
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580 million packets and counting, zero errors or lost packets


1/4/16
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420 million packets and counting, zero errors or lost packets
Reduced unused logic warnings by optimising phy startup logic (not tested yet)


31/3/16
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200 million packets and counting, zero errors or lost packets


30/3/16
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All commands working in simulation but in hardware functionality is sporadic
Moved message parser and as much of packet parser as possible to clk zone, minimising
logic clocked from PHY signals (also reduces FIFO use by getting rid of "glue" logic between
message parser and command parser)
Discovered that PhyTxEr absolutely must not be left floating
Set Tx OBUFS to fast slew rate
Removed inter-clock TIG's because they were causing sys_clk constraint to be ignored
Fixed pre-existing bug in phy_controller after moving it to clk zone
Finally working properly, 10 million packets with zero errors or packets lost


28/3/16
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Fixed non-padded CRC calculation (still need to check packets around minimum non-padded size, and not
just for multiples of eight bytes)
Fixed ghost command replies
Logic still hanging very quickly, maybe because Tx logic can't keep up, and bad packets are being found


27/3/16
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Fixed UDP padded packet CRC calculation
Got UDP commands working but with additional ghost command reply
Non-padded UDP packets not working


26/3/16
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CRC problems down to latency - does ARP CRC calculation even work in original packet_parser?
Fixed ARP CRC calculation
Fixed ICMP CRC calculation


25/3/16
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Arty project has same hang problem after ~440 million packets
Decided to cut out the FIFO buffering and deal with the split bytes directly in packet_parser (file now
called packet_parser_4bit.vhdl)
Started with rx data
Got ARP working but all CRC-dependent packets decoding not


21/3/16
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Fixed problem with rx_clk and clk_i timing constraints being ignored - bad packets and rx packet loss
are clear indicators of bad timing. Still getting hang, almost certainly when tx_clk and rx_clk are in anti-phase


12/3/16
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Added clock_wiz for clock input
Changed command_processor to run off principle clock with FIFO clock zone decoupling


11/3/16
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Fixed error propagation in EnetStats_CmdAndResponse


9/3/16
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Added automatic re-negotiation to Full duplex and removed delays


8/3/16
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Realised that interface defaults to half-duplex at start-up, meaning that problems are
almost certainly collision-related
Implemented SMI reading and writing working, successfully re-negotiated to 100Mbps Full duplex
Started moving phy_controller to top level with message_parser interface


6/3/16
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Added timing according to PC link speed
Separated LabVIEW into two separate projects, generic Phy100 and specific NexysPhy
Enforced IOB clocking to tx and rx signals but still getting very occasional bad packet


14/2/16
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Migrated to numeric_std


6/2/16
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Added sys_clk to drive reset of PHY
Added 7-segment display logic with firmware version as default on boot


5/2/16
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Got comms working


4/2/16
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Created project, not yet compilable (need to implement half-width Tx/Rx bus logic)
