Can this logic be used with non-Xilinx
hardware?
There is no reason why not. The only hardware-specific IP used is
the clock generator which should be easy to substitute. However the
user will need to understand how to provide appropriate constraints
and make sure that input and output registers are located in the
IOB's.
Can this logic be used without LabVIEW?
Definitely, communication is a simple exchange of UDP packets.
What is an acceptable rate of packet loss?
Both the Nexys3 and Arty3 projects ran continously for three days using the
Workout VI's for a total of 500 million packets exchanged and zero
packet loss.
What is an acceptable rate of communication
packet loss?
ML605-based projects have exceeded 1 Terabyte of packet exchange
with zero packet loss.