The Phy100 logic was derived from the GbPhy logic in order to be able to work with cheaper hardware. The event transmission logic has been removed to minimise hardware resources, with a result of occupying less than 30% of the Spartan 6 xc6slx16 used on the Digilent Nexys 3 evaluation board and less than 20% of the Artix 7 xc7a35t used on the Digilent Arty evaluation board. Both boards have a PHY which provides 4-bit data buses clocked at 25MHz.